lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 136

• Manufacturer Part Number: lan9313
• Description: Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
10.2
IEEE 1588 CLOCK MODE
0
The LAN9313/LAN9313i contains three identical IEEE 1588 Time Stamp blocks as shown in
Figure
64-bit IEEE 1588 clock time upon detection of a Sync or Delay_Req message type on their respective
port. The mode of the clock (master or slave) determines which message is detected on receive and
transmit. For slave clock operation, Sync messages are detected on receive and Delay_Req messages
on transmit. For master clock operation, Delay_Req messages are detected on receive and Sync
messages on transmit. Follow_Up, Delay_Resp and Management packet types do not cause capture.
Each port may be individually configured as an IEEE 1588 master or slave clock via the master/slave
bits (M_nS_1 for Port 1, MnS_2 for Port2, and M_nS_MII for Port 0) in the
(1588_CONFIG).
1588 clock operation.
For ports 1 and 2, receive is defined as data from the PHY (from the outside world) and transmit is
defined as data to the PHY. This is consistent with the point-of-view of where the partner clock resides
(LAN9313/LAN9313i receives packets from the partner via the PHY, etc.). For the time stamp module
connected to the external MII port (Port 0), the definition of transmit and receive is reversed. Receive
is defined as data from the switch fabric, while transmit is defined as data to the switch fabric. This is
consistent with the point-of-view of where the partner clock resides (LAN9313/LAN9313i receives
packets from the partner via the switch fabric, etc.).
As defined by IEEE 1588, and shown in
leading edge of the first data bit following the Start of Frame Delimiter (SFD). However, since the
packet contents are not yet known, the time stamp can not yet be loaded into the capture register.
Therefore, the time stamp is first stored into a temporary internal holding register at the start of every
packet.
IEEE 1588 Time Stamp
Preamble
(M_nS_x = 0)
(M_nS_x = 1)
1
Octet
Master
Slave
0
10.1. These blocks are responsible for capturing the source UUID, sequence ID, and current
1
0
Figure 10.2 IEEE 1588 Message Time Stamp Point
Table 10.1
Table 10.1 IEEE 1588 Message Type Detection
1
0
1
Start of Frame
summarizes the message type detection under slave and master IEEE
Message Timestamp
Delimiter
Ethernet
0
DATASHEET
1
Point
bit time
0
Figure
136
Delay_Req
RECEIVE
1 1 1
Sync
10.2, the message time stamp point is defined as the
0 0 0 0 0 0 0
Three Port 10/100 Managed Ethernet Switch with MII
0 0 0 0 0 0
Start of Frame
First Octet
following
1588 Configuration Register
SMSC LAN9313/LAN9313i
TRANSMIT
Delay_Req
Sync
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