lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 39

• Manufacturer Part Number: lan9313
• Description: Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
• Manufacturer: Standard Microsystems Corp.

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
77-79,
PIN
108
PIN
107
105
106
82
63
71
75
Note 3.14 The input buffers are enabled when configured as GPIO inputs only.
System Reset
Power Supply
Crystal Input
Purpose I/O
PLL +1.8V
Interrupt
General
Crystal
Output
Output
NAME
NAME
Test 1
Test 2
Input
Data
VDD18PLL
GPIO[11:8]
SYMBOL
SYMBOL
TEST1
TEST2
nRST
IRQ
XO
XI
Table 3.8 Miscellaneous Pins
Table 3.9 PLL Pins
DATASHEET
IS/OD12/
BUFFER
BUFFER
Note 3.14
O8/OD8
OCLK
TYPE
TYPE
ICLK
(PU)
(PU)
O12
AI
AI
IS
P
39
General Purpose I/O Data: These general
purpose signals are fully programmable as either
push-pull outputs, open-drain outputs, or Schmitt-
triggered inputs by writing the
Configuration Register (GPIO_CFG)
Purpose I/O Data & Direction Register
(GPIO_DATA_DIR). For more information, refer to
Chapter 12, "GPIO/LED Controller," on page
Note:
Interrupt Output: Interrupt request output. The
polarity, source and buffer type of this signal is
programmable via the
Register
Chapter 5, "System Interrupts," on page
System Reset Input: This active low signal allows
external hardware to reset the LAN9313/LAN9313i.
The LAN9313/LAN9313i also contains an internal
power-on reset circuit. Thus, this signal may be left
unconnected if an external hardware reset is not
needed. When used, this signal must adhere to the
reset timing requirements as detailed in
14.5.2, "Reset and Configuration Strap Timing," on
page
Test 1: This pin must be tied to VDD33IO for
proper operation.
Test 2: This pin must be tied to VDD33IO for
proper operation.
PLL +1.8V Power Supply: This pin must be
connected to VDD18CORE for proper operation.
Refer to the LAN9313/LAN9313i application note
for additional connection information.
Crystal Input: External 25MHz crystal input. This
signal can also be driven by a single-ended clock
oscillator. When this method is used, XO should be
left unconnected.
Crystal Output: External 25MHz crystal output.
390.
(IRQ_CFG). For more information, refer to
The remaining GPIO[7:0] pins share
functionality with the LED output pins, as
described in
DESCRIPTION
DESCRIPTION
Table 3.1
Interrupt Configuration
General Purpose I/O
Revision 1.2 (04-08-08)
and
Table
and
Section
52.
General
3.2.
142.