lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 189

• Manufacturer Part Number: lan9313
• Description: Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
• Manufacturer: Standard Microsystems Corp.

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
13.1.4.23
31:25
BITS
15:9
24
23
22
21
20
19
18
17
16
8
7
6
5
4
RESERVED
1588 Port 2 RX Interrupt Enable (1588_PORT2_RX_EN)
1588 Port 2 TX Interrupt Enable (1588_PORT2_TX_EN)
1588 Port 1 RX Interrupt Enable (1588_PORT1_RX_EN)
1588 Port 1 TX Interrupt Enable (1588_PORT1_TX_EN)
1588 Port 0(External MII) RX Interrupt Enable (1588_MII_RX_EN)
1588 Port 0(External MII) TX Interrupt Enable (1588_MII_TX_EN)
GPIO9 1588 Interrupt Enable (1588_GPIO9_EN)
GPIO8 1588 Interrupt Enable (1588_GPIO8_EN)
1588 Timer Interrupt Enable (1588_TIMER_EN)
RESERVED
1588 Port 2 RX Interrupt (1588_PORT2_RX_INT)
This interrupt indicates that a packet received by Port 2 matches the
configured PTP packet and the 1588 clock was captured.
1588 Port 2 TX Interrupt (1588_PORT2_TX_INT)
This interrupt indicates that a packet transmitted by Port 2 matches the
configured PTP packet and the 1588 clock was captured.
1588 Port 1 RX Interrupt (1588_PORT1_RX_INT)
This interrupt indicates that a packet received by Port 1 matches the
configured PTP packet and the 1588 clock was captured.
1588 Port 1 TX Interrupt (1588_PORT1_TX_INT)
This interrupt indicates that a packet transmitted by Port 1 matches the
configured PTP packet and the 1588 clock was captured.
1588 Port 0(External MII) RX Interrupt (1588_MII_RX_INT)
This interrupt indicates that a packet from the switch fabric to the External
MII the matches the configured PTP packet and the 1588 clock was
captured.
Note:
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)
This read/write register contains the IEEE 1588 interrupt status and enable bits.
Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these
interrupt bits are cascaded into bit 29 (1588_EVNT) of the
a 1 to any of the interrupt enable bits will enable the corresponding interrupt as a source. Status bits
will still reflect the status of the interrupt source regardless of whether the source is enabled as an
interrupt in this register. Bit 29 (1588_EVNT_EN) of the
be set in order for an actual system level interrupt to occur. Refer to
on page 52
For Port 0, receive is defined as data from the switch fabric, while
transmit is to the switch fabric.
Offset:
for additional information.
198h
DESCRIPTION
DATASHEET
189
Size:
Interrupt Enable Register (INT_EN)
Interrupt Status Register
32 bits
Chapter 5, "System Interrupts,"
R/WC
R/WC
R/WC
R/WC
R/WC
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Revision 1.2 (04-08-08)
(INT_STS). Writing
DEFAULT
must also
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
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-