lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 111

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

OBF
6.11.7 EXTERNAL CLOCK SIGNAL
The LPC47S45x Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock. The reset
pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to both internally (Vcc POR)
and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip.
6.11.8 DEFAULT RESET CONDITIONS
The LPC47S45x has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer to Table 55 for
the effect of each type of reset on the internal registers.
GATEA20 And Keyboard Reset
The LPC47S45x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and
KRESET and Port 92 Fast GateA20 and KRESET.
Port 92 Fast GATEA20 and Keyboard Reset
Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical
Device 7, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
SMSC LPC47S45x
BIT
7:6
5
4
3
2
1
reads the input data register (DBB), this bit is automatically reset and the interrupt is cleared. There is no
output pin associated with this internal signal.
(Output Buffer Full) - This flag is set to whenever the LPC47S45x CPU write to the output data register (DBB).
When the host system reads the output data register, this bit is automatically reset.
Reserved. Returns 00 when read
Reserved. Returns a 1 when read
Reserved. Returns a 0 when read
Reserved. Returns a 0 when read
Reserved. Returns a 1 when read
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a 1
to this bit causes the ALT_A20 signal to be driven high.
N/A: Not Applicable
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
DESCRIPTION
NAME
LOCATION
DEFAULT
VALUE
ATTRIBUTE
SIZE
DATASHEET
PORT 92 REGISTER
Table 55 − Resets
Page 111 of 259
FUNCTION
Port 92
92h
24h
Read/Write
8 bits
HARDWARE RESET
(PCI_RESET#)
Low
Low
Low
Low
00H
N/A
Rev. 08-10-09