lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 122

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

6.12.7 LED FUNCTIONALITY
The LPC47S45x provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn
the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D
and 0x5E from the base address located in the primary base I/O address in Logical Device A.
The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed.
In order to control an LED while the part is under VTR power, the GPIO pin must be configured for the LED function
and either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking
current to control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to
blink the LED under VTR power. The LED will not blink under VTR power (VCC removed) if an external 32kHz clock
source is not connected.
The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is powered by either
VCC or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current
from VTR even when VCC is present.
The LED control registers are defined in the “Runtime Register” section.
6.13 Watch Dog Timer
The LPC47S45x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an
interrupt through the WDT_CFG Runtime Register.
The LPC47S45x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1
to 255 seconds with 1 second resolution.
The units of the WDT timeout value are selected via bit[7] of the
WDT_TIMEOUT register (Runtime Register at offset 0x52). The WDT time-out value is set through the WDT_VAL
Runtime register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its power on default).
Setting the WDT_VAL to any other non-zero value will cause the WDT to reload and begin counting down from the
value loaded. When the WDT count value reaches zero the counter stops and sets the Watchdog time-out status bit
in the WDT_CTRL Runtime register. Note: Regardless of the current state of the WDT, the WDT time-out status bit
can be directly set or cleared by the Host CPU.
There are three system events which can reset the WDT. These are a Keyboard Interrupt, a Mouse Interrupt, or
I/O reads/writes to address 0x201. The effect on the WDT for each of these system events may be individually
enabled or disabled through bits in the WDT_CFG Runtime register. When a system event is enabled through the
WDT_CFG register, the occurrence of that event will cause the WDT to reload the value stored in WDT_VAL and
reset the WDT time-out status bit if set. If all three system events are disabled the WDT will inevitably time out.
The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the Time-out status bit. The
WDT interrupt is mapped to an interrupt channel through the WDT_CFG Runtime register. When mapped to an
interrupt the interrupt request pin reflects the value of the WDT time-out status bit.
The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out)
Runtime register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL
(Watch Dog Status). Bit 2 of the WDT_CTRL is self-clearing.
See the Runtime Registers section for description of these registers.
SMSC LPC47S45x
Page 122 of 259
Rev. 08-10-09
DATASHEET