lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 133

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

Default =
0x00 on VTR
POR, VCC
POR,
PCI Reset or
Soft Reset
OWN ADDR
Bit 0 nBB
Bus Busy bit. This is a read-only flag indicating when the SMBus is in use. A zero indicates that the bus is busy, and
access is not possible. This bit is set/reset (logic “1”/logic “0”) by Start/Stop conditions.
Own Address Register
When the chip is addressed as slave, this register must be loaded with the 7-bit SMBus address to which the chip is
to respond. During initialization, the own address register must be written to, regardless whether it is later used. The
Addressed As Slave (AAS) bit in status register is set when this address is received (the value in the data register is
compared with the value in own address register). Note that the data and own address registers are offset by one bit;
hence, programming the own address register with a value of 55h will result in the value AAh being recognized as the
chip’s SMBus slave address.
Data Shift Register
The Data Register acts as serial shift register and read buffer interfacing to the SMBus. All read and write operations
to/from the SMBus are done via this register. SMBus data is always shifted in or out of shift register.
In receiver mode the SMBus data is shifted into the shift register until the acknowledge phase. Further reception of
data is inhibited (SCLK pin held low) until the data shift register is read.
In the transmitter mode data is transmitted to the SMBus as soon as it is written to the shift register if the serial I/O is
enabled (ESO=1).
Note: Bytes are transferred most significant bit (MSB) first.
Clock Register
Overview
The Clock Register controls the internal SMBus clock generator, the SMBus reset, and the SCLK pin clock frequency
(Table 67). The Clock register is 00H by default.
Note 1: The SMBus reset bit is not self-clearing.
SMSC LPC47S45x
NAME
TYPE
After reset, own address register has default address 00h.
0x00 on VTR POR,
VCC POR,
PCI Reset or
Soft Reset
SMB_RST
Bit Def
(Note 1)
Default
Type
Bit
R/W
D7
Table 65 − SMBus Own Address Register (SMBus Base Address +1)
Address
(bit 6)
Table 67 − SMBus Clock Register (SMBus Base Address +3)
Slave
R/W
Table 66 − SMBus Data Register (SMBus Base Address +2)
D7
D6
R
R/W
DATA
RESERVED
D5
R
Address
(bit 5)
Slave
R/W
D6
D4
R
R/W
D7
DATASHEET
D3
R
Address
Slave
(bit 4)
R/W
R/W
Page 133 of 259
D5
D6
CLK_DIV
R/W
D2
R/W
D5
Address
(bit 3)
Slave
R/W
D4
CLK_SEL
R/W
D4
R/W
D1
Address
(bit 2)
Slave
R/W
D3
R/W
D3
RESERVED
Address
R/W
Slave
(bit 1)
D2
R/W
D0
R
D2
R/W
D1
Address
Slave
(bit 0)
R/W
D1
PCI Reset or
VCC POR,
VTR POR,
DEFAULT
Soft Reset
0x00 on
R/W
D0
Rev. 08-10-09
Command
Read = ‘1’
Write = ‘0’
R/W
D0
Bit