lpc4310 NXP Semiconductors, lpc4310 Datasheet - Page 39

• Manufacturer Part Number: lpc4310
• Description: Lpc4350/30/20/10 32-bit Arm Cortex-m4/m0 Mcu; Up To 264 Kb Sram; Ethernet; Two High-speed Usbs; Advanced Configurable Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.12.6.1 Features
7.12.7.1 Features
7.12.7 LCD controller
The USB1 interface can operate as a full-speed USB Host/Device interface or can
connect to an external ULPI PHY for High-speed operation.
Remark: Not available on all parts and packages. See
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 × 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
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Complies with Universal Serial Bus specification 2.0.
Complies with Enhanced Host Controller Interface Specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
Supports all full-speed USB-compliant peripherals.
Supports interrupts.
This module has its own, integrated DMA engine.
AHB master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
Supports single and dual-panel color STN displays.
Supports Thin Film Transistor (TFT) color displays.
Programmable display resolution including, but not limited to: 320 × 200, 320 × 240,
640 × 200, 640 × 240, 640 × 480, 800 × 600, and 1024 × 768.
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized for color STN and TFT.
24 bpp true-color non-palettized for color TFT.
Programmable timing for different display panels.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 October 2010
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
Table
2.
© NXP B.V. 2010. All rights reserved.
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