lpc4310 NXP Semiconductors, lpc4310 Datasheet - Page 42

• Manufacturer Part Number: lpc4310
• Description: Lpc4350/30/20/10 32-bit Arm Cortex-m4/m0 Mcu; Up To 264 Kb Sram; Ethernet; Two High-speed Usbs; Advanced Configurable Peripherals
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.13.4.1 Features
7.13.5.1 Features
7.13.4 SSP0/1 serial I/O controllers
7.13.5 I
The LPC4350/30/20/10 contain two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
The LPC4350/30/20/10 each contain two I
The I
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
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C0/1-bus interfaces
Maximum SSP speed of <tbd> Mbit/s (master) or <tbd> Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
I
supports Fast mode plus with bit rates up to 1 Mbit/s.
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
All I
2
2
2
C0 is a standard I
C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
2
C-bus controllers support multiple address recognition and a bus monitor mode.
2
C-bus can be used for test and diagnostic purposes.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 October 2010
2
C compliant bus interface with open-drain pins. I
2
C-bus controllers.
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
2
C is a multi-master bus and can be
2
© NXP B.V. 2010. All rights reserved.
C-bus).
2
C0 also
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