hip9010 Intersil Corporation, hip9010 Datasheet - Page 10

• Manufacturer Part Number: hip9010
• Description: Engine Knock Signal Processor
• Manufacturer: Intersil Corporation

The digital block diagram shows the programming flow of the
chip. An eight bit word is received at the MISO port. Data is
shifted in by the SCK clock when the chip is enabled by the
CS pin. The word is decoded by the address decoding
circuit, and the information is directed to one of 5 registers.
These registers control:
A crystal oscillator circuit is provided. The chip requires a 4MHz
crystal to be connected across OSCIN and OSCOUT pins.
In the test mode, use the digital multiplexer to output one of
the following signals:
1. Reference knock filter frequency.
2. Knock filter frequency.
3. Balance control or attenuation of one channel with
4. Integration time constant of the sum of the two channels.
5. One of 3 functions.
1. Contents of one of the five registers in the chip.
2. Inverted signal of the MOSI pin.
3. Voltage of an internal comparator used to rectify the
respect to the other.
a) test conditions of the part.
b) channel select to one of two sensors.
c) channel to be attenuated.
analog signal.
MOSI
SCK
CS
4-10
ADDRESS DECODER
OSCIN
OSCILLATOR
CIRCUIT
FIGURE 5. DIGITAL BLOCK DIAGRAM
TEST/ CHANNEL SELECT ATTENUATE
INTEGRATOR TIME CONSTANT
OSCOUT
REFERENCE FILTER
BALANCE CONTROL
HIP9010
KNOCK FILTER
COMPARATOR OUT
(FROM RECTIFIER PHASE
DETECTOR)
Upon power up, chip requires that the INT/HOLD pin is
toggled. If this is not done then it is important to note, that
only the first result and SPI data bytes sent after power up
will not be valid. Any subsequent chip operation will then be
performed correctly.
T1 minimum time from CS falling edge to SCK falling edge.
T2 minimum time from CS falling edge to SCK rising edge.
T3 minimum time for the SCK low.
T4 minimum time for the SCK high.
T5 minimum time from SCK rise after 8 bits to CS rising edge.
T6 minimum time from data valid to rising edge of SCK.
T7 minimum time for data valid after the rising edge of the
SCK.
T8 minimum time after CS rises until INT/HOLD goes high.
DATA IN
T1
SCK
INT/HOLD
CS
T2
T6
MOSI
TEST
TABLE 3. SPI TIMING REQUIREMENTS
B7
T4
B6
T7
T3
FIGURE 6. SPI TIMING
DESCRIPTION
B5
B4
MISO
B3
B2
B1
T5
B0
T8
UNITS
10ns
80ns
60ns
60ns
80ns
60ns
10ns
8 s