hip9010 Intersil Corporation, hip9010 Datasheet - Page 7

• Manufacturer Part Number: hip9010
• Description: Engine Knock Signal Processor
• Manufacturer: Intersil Corporation

Balance/Gain Adjust Stage
The gains from the Knock Frequency Filter and the
Reference Frequency Filter can be adjusted with respect to
one another, so that the difference energies in the two bands
can be compensated. This balance is achieved by feeding
one of the filters unattenuated (gain = 1) and attenuating the
other. This can be adjusted with 64 different gain settings,
ranging between 1 and 0.133. The signals can swing
between 20 and 80 percent of V
Programming is discussed in the Communications Protocol
section. The test/channel attenuate word is used to
determine which of the two channels is attenuated and
which is set to unity gain.
Active Full Wave Rectifier
The output of the filters are independently full wave rectified
using switch capacitor techniques. Each of two rectifier
circuits provide both negative and positive values for the
knock frequency and reference frequency filter outputs. The
output is able to swing from 20% to 80% of V
taken to minimize the RMS variations from input to output of
this section.
Integrator Stage
The signals from the two rectifiers are summed and
integrated together. A differential system is used to reduce
noise. One system integrates the positive energy of the
Knock Frequency Rectifier with respect to the positive
energy of the Reference Frequency Rectifier. The second
system does the integration of the negative energy value of
the two rectifiers. The positive and negative energy signals
are opposite phase signals. Using this technique reduces
system noise.
The integrator time constant is software programmable by
the Integrator Time Constant discussed in the
Communications Protocol section. The time constant can be
programmed from 40 s to 600 s, with a total of 32 steps. If
for example, we program a time constant to 200 s, then with
one volt difference between each channel, the output of the
integrator will change by 1 volt in 200 s.
When integration is enabled by the rising edge of the
INT/HOLD input, the output of the integrator will fall to 0.5V,
within 20 s after the integrate line reaches the integrate
state. The output of the integrator is an analog voltage.
Test Multiplexer
This circuit receives the positive and negative outputs from
the two integrators, together with the outputs from different
parts of the IC. The output is controlled by the fifth
programming word of the communications protocol. This
multiplexes the switch capacitor filter output, the gain control
output and the antialiasing filter output.
4-7
DD
.
DD
. Care was
HIP9010
Differential to Single-Ended Converter
This signal takes the output of the two integrators (through
the test-multiplexer circuit) and provides a signal that is the
sum of the two signals. This technique is used to improve the
noise immunity of the system.
Output Buffer
This output amplifier is the same amplifier circuits as the
input amplifier used to interface with the sensors. When the
output of the antialiasing filter is tested, this amplifier is in the
power down mode.
Communications Protocol
The multiprocessor talks to the knock sensor via an SPI
bus (MOSI). A chip select pin (CS) is used to enable the
chip, which, in conjunction with the SPI clock (SCK), moves
in the eight bit programming word. Five different
programming words are used to set gains, frequency
response, integrator constants, test mode, channel select
and test mode conditions.
With chip select (CS) going low, on the next rising edge of
the SPI clock (SCK), data is latched into the IC. The data is
shifted with the most significant bit first and least significant
bit last. Each word is divided into two parts: first the address
and then the value. Depending on the function being
controlled, the address is 2 or 3 bits, and the value is either 5
or 6 bits long. During the hold mode of operation, all five
programming words can be entered into the IC, but during
the integrate time any single byte may be entered but will not
be acted upon until the start of the next hold period. The
integration or hold mode of operation is controlled by the
INT/HOLD input signal.
Programming Words
1. Reference Filter Frequency: Defines the center frequency
2. Knock Filter Frequency: Defines the center frequency of
3. Balance Control: Defines the ratio of the gain of the knock
of the Reference Filter in the system. The first 2 bits are
used for the address and the last 6 bits are used for its
value. 01FFFFFF Example: 01001010 would be the
reference filter (01 for the first two bits) at a center
frequency of 1.78kHz (bit value in Table 2 of 10).
the Knock Filter in the system. The first 2 bits are used for
the address and the last 6 bits are used for its value.
00FFFFFF Example: 00100111 would be the knock filter
frequency (00 for the first two bits) at a center frequency
of 6.37kHz (bit value in Table 2 of 39).
band center frequency to that of the reference band
center frequency. This role can be reversed by the value
of C
Test/Channel Select/Channel Attenuate Control. The first
2 bits are used for the address and the last 6 bits for its
value. 10GGGGGG Example: 10010100 would be the
balance control (10 for the first two bits) with an
attenuation of 0.514 (bit value in Table 2 of 20.)
Depending on the value of C
apply to the reference or the knock gain section.
A
in the fifth programming bit, as explained in 5,
A
in the fifth word this would