hip9010 Intersil Corporation, hip9010 Datasheet - Page 11

• Manufacturer Part Number: hip9010
• Description: Engine Knock Signal Processor
• Manufacturer: Intersil Corporation

T1 maximum rise time of the INT/HOLD signal.
T2 maximum time after INT/HOLD rises for the INOUT to
begin to intergrate.
T3 maximum fall time of INT/HOLD signal.
T4 typical time after INT/HOLD goes low before chip
goes into hold state.
T5 minimum INT/HOLD time during power up sequence.
INT/HOLD
INTOUT
TABLE 4. INTERGRATE/HOLD TIMING REQUIREMENTS
INT/HOLD
T1
CS
T2
FIGURE 7. POWER UP SEQUENCE
FIGURE 8. INTEGRATOR TIMING
DESCRIPTION
4-11
T3
T4
UNITS
45ns
20 s
45ns
20 s
1 s
HIP9010
Test Multiplexer
This circuit receives the positive and negative outputs out of
the two integrators, together with the outputs from different
parts of the chip. The output is controlled by the fifth
programming word of the communications protocol. This
multiplexes the switch capacitor filter output, the gain control
output as well as the antialias output.
Differential to Single-ended Converter
This signal takes the output of the two integrators (through
the test multiplexer circuit) and provides a signal that is the
sum of the two signals. This technique is used to improve the
noise immunity of the system.
Output Buffer
This output amplifier is the same as the input amplifier used
to interface to the sensors. For test purposes when we look
at the output of the antialias filter, the input amplifiers are in
the power down mode.