aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 11

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aduc7033bstz-8l-rl

Manufacturer Part Number
aduc7033bstz-8l-rl
Description
Integrated Precision Battery Sensor For Automotive
Manufacturer
Analog Devices, Inc.
Datasheet
Table 3. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SCLK
SCLK
MOSI
MISO
t
DOSU
1
t
1
DSU
MSB IN
MSB
t
DHD
t
SH
Figure 3. SPI Master Mode Timing (PHASE Mode = 0)
2
t
DF
HCLK
2
t
DAV
= t
UCLK
t
SL
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CD
t
DR
.
BITS [6:1]
BITS [6:1]
Min
0
3 × t
UCLK
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
3.5
3.5
3.5
3.5
½ t
SL
LSB IN
t
SR
LSB
HCLK
HCLK
t
SF
Max
(2 × t
UCLK
) + (2 × t
HCLK
ADuC7033
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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