aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 113

• Manufacturer Part Number: aduc7033bstz-8l-rl
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

SPI Control Register
Name:
Address:
Default Value:
Access:
Function:
Table 89. SPICON MMR Bit Designations
Bit
15 to 13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPICON
0xFFFF0A10
0x0000
Read/write
The 16-bit MMR configures the serial peripheral interface.
Description
Reserved.
Continuous Transfer Enable.
Loopback Enable.
Slave Output Enable.
Slave Select Input Enable.
SPIRX Overflow Overwrite Enable.
SPITX Underflow Mode.
Transfer and Interrupt Mode (Master Mode).
LSB First Transfer Enable Bit.
Reserved. Should be written as 0.
Serial Clock Polarity Mode Bit.
Serial Clock Phase Mode Bit.
Master Mode Enable Bit.
SPI Enable Bit.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, a new transfer is initiated after a stall period.
Set by user to connect MISO to MOSI and test software.
Cleared by user to be in normal mode.
Set by user to enable the slave output.
Cleared by user to disable slave output.
Set by user in master mode to enable the output.
Set by the user, the valid data in the SPIRX register is overwritten by the new serial byte received.
Cleared by the user, the new serial byte received is discarded.
Set by the user to transmit the previous data.
Cleared by the user to transmit 0.
Set by the user to initiate a transfer with a write to the SPITX register. Interrupt occurs when SPITX is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. Interrupt occurs when SPIRX is full.
Set by the user; the LSB is transmitted first.
Cleared by the user; the MSB is transmitted first.
Set by user, the serial clock idles high.
Cleared by user the serial clock idles low.
Set by the user. The serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user. The serial clock pulses at the end of each serial bit transfer.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
Set by the user to enable the SPI.
Cleared to disable the SPI.
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ADuC7033