aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 50

• Manufacturer Part Number: aduc7033bstz-8l-rl
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7033
Current Channel ADC Control Register
Name:
Address:
Default Value:
Access:
Function:
Note:
Table 37. ADC0CON MMR Bit Designations
Bit
15
14, 13
12 to 10
9
Bit
2 to 0
Description
ADC Operation Mode Configuration.
ADC0CON
0xFFFF050C
0x0000
Read/write
The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC.
If the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset.
Description
Current Channel ADC Enable.
IIN Current Source Enable.
Not Used. These bits are reserved for future functionality and should be written as zero.
Current Channel ADC Output Coding.
000 = ADC power-down mode. All ADC circuits (including internal reference) are powered-down.
001 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts.
010 = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle
mode when the single shot conversion is complete. A single conversion takes two to three ADC clock cycles depending on
the chop mode.
011 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset.
100 = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using an
internally generated 0 V. The calibration is carried out at the user programmed ADC settings; therefore, as with a
normal single ADC conversion, it takes two to three ADC conversion cycles before a fully settled calibration result is
ready. The calibration result is automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to
idle mode and the calibration and conversion ready status bits are set at the end of an offset calibration cycle.
101 = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is performed on
all enabled ADCs. A gain calibration is a two-stage process and takes twice the time of an offset calibration. The
calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to idle mode
and the calibration and conversion ready status bits are set at the end of a gain calibration cycle. An ADC self-gain
calibration should only be carried out on the current channel ADC. Use the preprogrammed, factory calibration
coefficients (downloaded automatically from internal Flash/EE memory) for voltage temperature measurements. If an
external NTC is used, an ADC self-calibration should be performed on the temperature channel.
110 = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels
against an external zero-scale voltage driven at the ADC input pins. The calibration is carried out at the user
programmed ADC settings; therefore, as with a normal, single ADC conversion, it takes three ADC conversion cycles before
a fully settled calibration result is ready.
111 = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels
against an external full-scale voltage driven at the ADC input pins.
Set to 1 by user code to configure I-ADC output coding as unipolar.
Cleared to 0 by user code to configure I-ADC output coding as twos complement.
Set to 1 by user code to enable the I-ADC.
Clearing this bit to 0 powers down the I-ADC and resets the respective ADC ready bit in the ADCSTA MMR to 0.
00 = current sources off.
01 = enables 50 μA current source on IIN+.
10 = enables 50 μ A current source on IIN−.
11 = enables 50 μ A current source on both IIN− and IIN+.
10 = ADC low power plus mode. If enabled, the ADC operates with reduced current consumption. In this mode, the
gain is fixed to 512 and the current consumed is approximately 200 μA more than the ADC low power mode. The
additional current consumed also ensures that the ADC noise performance is better than that achieved in ADC low
power mode.
11 = not defined.
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