pi2eqx5864 Pericom Semiconductor Corporation, pi2eqx5864 Datasheet - Page 3

• Manufacturer Part Number: pi2eqx5864
• Description: 5.0gbps 4-lane Pcie Gen2 Redriver With I2c Control
• Manufacturer: Pericom Semiconductor Corporation

DESCRIPTION of OPERATION
Confi guration Modes
Device confi guration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC
confi guration status is from the input pins or via I2C control. When MODE is set high, the confi guration input pins set the confi gura-
tion operating state as stored in confi guration registers. While MODE is set high, changes to these control registers are disabled and
the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low, reprogramming
of these control registers via I2C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable I2C
access.
During initial power-on, the value at the confi guration input pins: LB#, RES_A#, RES_B#,RXD_A and RXD_B, will be latched to
the confi guration registers as initial startup states.
Equalizer Confi guration
The PI2EQX5864 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal
traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either
too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application.
Equalizer confi guration can be programmed via I
equalization control, and all four channels within the group are assigned the same confi guration state. The Equalizer Selection table
below describes the register state and associated operation of the equalizer.
Equalizer Selection
54
24
50
22
53
52
55, 56, Center Pad
1, 6, 11, 16, 21, 29,
34, 39, 44, 49
SEL2_[A:B]
0
0
0
0
1
1
1
1
07-0277
RES_A#
RES_B#
RXD_A
RXD_B
SCL
SDA
GND
VDD
SEL1_[A:B]
0
0
1
1
0
0
1
1
I
I
I
I
I/O
I/O
PWR
PWR
2
C when the mode pin is low. Each group of four channels, A and B, has separate
RES_A# is an active low channel reset input for Channel A0, A1, A2 and A3 with
internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset,
and normal detection cycle is carry on after the pin goes high.
RES_B# is an active low channel reset input for Channel B0, B1, B2 and B3 with
internal 100K-Ohm pull-up resistor. When low, receiver detection cycle is reset,
and normal detection cycle is carry on after the pin goes high.
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100K-
Ohm pull-up resistor.
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor.
I
I
Supply Ground
1.2V Supply Voltage
2
2
C SCL clock input. Up to 3.3V input tolerance.
C SDA data input. Up to 3.3V input tolerance
SEL0_[A:B]
0
1
0
1
0
1
0
1
3
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
PS8934A
PI2EQX5864
2
C Control
01/21/08