pi2eqx5864 Pericom Semiconductor Corporation, pi2eqx5864 Datasheet - Page 9

• Manufacturer Part Number: pi2eqx5864
• Description: 5.0gbps 4-lane Pcie Gen2 Redriver With I2c Control
• Manufacturer: Pericom Semiconductor Corporation

BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RES_A# & RES_B# inputs at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition from 0 to 1 initiates a
new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled). While static at 0 or 1, the RES_zy# bit will have
no effect on operation. The Channel Reset bits are read/write allowing the current state to be checked.
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the
channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When
RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is
enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer confi guration, Dx_A: Emphasis control, Sx_A: Output level control (see Confi guration Table)
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
Power-on
Power-on
Power-on
Power-on
Name
Name
Name
Name
Type
State
Type
State
State
State
Type
Type
Bit
Bit
Bit
Bit
07-0277
RES_A0#
PD_A0#
RXD_A0
SEL0_A
R/W
R/W
R/W
R/W
7
1
7
1
7
1
7
1
RES_B0#
PD_B0#
RXD_B0
SEL1_A
R/W
R/W
R/W
R/W
6
1
6
1
6
1
6
1
RES_A1#
PD_A1#
RXD_A1
SEL2_A
R/W
R/W
R/W
R/W
5
1
5
1
5
1
5
1
RES_B1#
PD_B1#
RXD_B1
R/W
R/W
D0_A
R/W
R/W
4
1
4
1
4
1
4
1
9
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I
RES_A2#
PD_A2#
RXD_A2
D1_A
R/W
R/W
R/W
R/W
3
1
3
1
3
1
3
1
RES_B2#
PD_B2#
RXD_B2
D2_A
R/W
R/W
R/W
R/W
2
1
2
1
2
1
2
1
RES_A3#
PD_A3#
RXD_A3
R/W
R/W
S0_A
R/W
R/W
1
1
1
1
1
1
1
1
PS8934A
PI2EQX5864
2
RES_B3#
RXD_B3
C Control
PD_B3#
S1_A
R/W
R/W
R/W
R/W
0
1
0
1
0
1
0
1
01/21/08