pi2eqx5864 Pericom Semiconductor Corporation, pi2eqx5864 Datasheet - Page 5

• Manufacturer Part Number: pi2eqx5864
• Description: 5.0gbps 4-lane Pcie Gen2 Redriver With I2c Control
• Manufacturer: Pericom Semiconductor Corporation

Receiver Detect
Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device
on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5864 to confi gure itself properly
depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card.
Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or RXD_B is set
to low, the Receiver Detect operation for that group of channels is disabled, and those channels go directly to 50-Ohm input termi-
nation to ground and 50-Ohm output termination to Vdd (for a valid differential channel input level) or to 2K-Ohm (if the signal
level is less than the threshold level).
The RES_A#, and RES_B# inputs are used to reset the receiver detect state machine to its initial state. RES_A# and RES_B#
control the received detect reset for the A and B group of channels respectively. The start of the receiver detect cycle starts when
RES_A# or RES_B# transitions from low to high.
When a Receiver Detect cycle begins the differential channel pins are enabled with a 2K-Ohm pullup to Vdd. A 50-Ohm Receiver
termination will change the pin level. This pin level is evaluated after a fi xed time-out, and the channel is then set into the proper
operating state. The register bits RX50_Ax and RX50_Bx represent the receiver detect result for their specifi c channels.
The I/O operation table summarizes the relationships and operation of receiver detect and other signals involved with I/O control.
I/O Operation Control
PD# PRSNT2# RXD_x RES_x#
0
1
1
1
1
1
1
1
1
07-0277
Control Inputs
X
1
0
0
0
0
0
0
0
X
X
0
0
0
1
1
1
1
X
X
0
1
1
0
1
1
1
RX50
X
X
X
X
X
X
0
1
1
Detection
States
SIG_x
X
X
X
X
X
0
1
0
1
Input Termination Output Termination
50-Ohm pull-
50-Ohm pull-
50-Ohm pull-
50-Ohm pull-
5
down
down
down
down
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Channel I/O
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I
2K-Ohm pull-up
2K-Ohm pull-up
2K-Ohm pull-up
2K-Ohm pull-up
2K-Ohm pull-up
50-Ohm pull-up
50-Ohm pull-up
Hi-Z
Hi-Z
Full IC power down, all chan-
ing. Receiver detect disabled.
enabled, no receiver detected.
Channel inactive, output pulls
pulls to Vdd. Receiver detect
pulls to Vdd. Receiver detect
ing. Receiver detect enabled,
Channel enabled, valid input
abled, receiver detected. No
signal detected, output driv-
signal detected, output driv-
Channel disabled. Receiver
to Vdd. Receiver detect en-
signal, output pulls to Vdd.
Channel active, valid input
Channel enabled, no input
Channel disabled, output
Channel disabled, output
Receiver detect disabled
PRSNT2#), all channels
No receiver (defi ned by
load detected.
nels disabled
detect reset.
input signal
disabled
PS8934A
Mode
reset
PI2EQX5864
2
C Control
01/21/08