ncn6804 ON Semiconductor, ncn6804 Datasheet - Page 10
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ncn6804
Manufacturer Part Number
ncn6804
Description
Dual Smart Card Interface Ic With Spi Programming Interface
Manufacturer
ON Semiconductor
Datasheet
1.NCN6804.pdf
(25 pages)
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PROGRAMMING
Write Register " WRT_REG (Is Low Only)
depicted in Tables 1 and 2. These bits are concatenated into 1 byte [MSB0,LSB0] in order to accelerate the programming
sequence. The register can be updated when CS is low only.
Table 1. WRT_REG BIT DEFINITIONS
8. When operating in Asynchronous mode, b6 is compared with the external voltage level present pin S1 (Pin 1).
9. The CRD_RST pin reflects the content of the MOSI WRT_REG [b4] during the chip programming sequence. Since the bit shall be Low
b0
b1
Similar to the NCN6001, the NCN6804's WRT_REG register handles 3 command bits [b5:b7] and 5 data bits [b0:b4] as
The WRT_RGT has been defined to be compatible with the NCN6001 write register.
to address the chip's internal register, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
If (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then
Else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then
Else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then
Else if (b7 + b6 + b5) =101 then
Else if (b7 + b6 + b5) =100 then
End if
Case 00
Case 01
Case 10
Case 11
Case 00
Case 01
Case 10
Case 11
b1 drives CRD_C4A or B (respectively)
b0 drives CRD_C8A or B (respectively)
Case 00
Case 01
Case 11
NA (Not Applicable)
Case 10
CRD_VCCA = 0 V
CRD_VCCA = 1.8 V
CRD_VCCA = 3.0 V
CRD_VCCA = 5.0 V
CRD_VCCB = 0 V
CRD_VCCB = 1.8 V
CRD_VCCB = 3.0 V
CRD_VCCB = 5.0 V
CRD_DET = NO
CRD_DET = NC
SPI_MODE = Special
SPI_MODE = Normal
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NCN6804
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