ncn6804 ON Semiconductor, ncn6804 Datasheet - Page 16

• Manufacturer Part Number: ncn6804
• Description: Dual Smart Card Interface Ic With Spi Programming Interface
• Manufacturer: ON Semiconductor

the I/O signal being Open Drain or Totem Pole on either
sides.
card system provisions have been made to avoid CRD_IOA
or B current overload. Depending upon the selected mode of
operation (Async. or Sync), the card I/O line is respectively
connected to either I/O Pin 25, or to the MOSI register byte
bit 2. On the other hand, the logic level present at the card I/O
is feedback to the micro-controller via the MISO register
bit 3. The logic levels present at Pin 31 (EN_RPU) controls
the connection of the internal pullup as depicted Table 6.
NOTE:
Table 6. I/O PULLUP RESISTOR TABLE
EN_RPU
The transaction is valid when the Chip Select pin is Low,
Since the device can operate either in a single or a multiple
From MOSI
decoding
High
Low
MOSI/b2
MOSI/b3
SYNC
EN_RPU
18 kW typical value
Internal 18 kW Pullup
V
I/O Pullup Resistor
CC
I/O
Disconnected
Open, 18 kW
9
GND
6
Active
1
Q5
U1
R1
Device Operation
Applicable in the
Multidevice Mode
Case
Single Device
Mode
18 k
CARD ENABLE
V
Figure 8. Basic I/O Internal Circuit
CC
Q1
SEQ 1
POR
http://onsemi.com
200 ns
NCN6804
16
Interrupt
HIGH upon Power On Reset (POR) signal. The interrupt
Pin 24 is forced LOW when a card is inserted or extracted
in either of the external ports, or when a fault is developed
across the CRD_VCC output voltage A or B. This signal is
neither combined with CS signal, nor with the chip address.
The INT signal is clear to HIGH upon one of the conditions
Table 7.
Figure 9. Typical I/O rise & fall time (CRD_IOA or B/
When the system is powered up, the INT Pin is set to
LEVEL SHIFT
Q3
LOGIC AND
Q4
C
out
> 30 pF and open-drain)
CRD_VCC
VCC
200 ns
Q2
GND
R2
Q5
18 k
13
20
CRD_VCC
CRD_IO