ncn6804 ON Semiconductor, ncn6804 Datasheet - Page 18

• Manufacturer Part Number: ncn6804
• Description: Dual Smart Card Interface Ic With Spi Programming Interface
• Manufacturer: ON Semiconductor

SPI Port
controller by means of a serial link using a Synchronous Port
Interface protocol, the CLK_SPI being Low or High during
the idle state. The NCN6804 is not intended to operate as a
Master controller, but executes commands coming from the
MPU.
microcontroller's responsibility. The MISO signal is
on the SPI port. The two data lines become active when
CS = Low, the internal shift register is cleared and the
communication is synchronized by the negative going edge
of the CS signal. THe data presents on the MOSI line are
considered valid on the negative going edge of the CLK_SPI
clock and is transferred to the shift register on the next
positive edge of the same CLK_SPI clock.
signal and the NCN6804 related functions are updated accordingly.
The product communicates to the external micro
The CLK_SPI, CS and MOSI signals are under the
When the CS line is High, no data can be written or read
When the bit transfer is completed, the content of the internal shift register is latched on the positive going edge of the CS
RST_COUNTER
ADDRESS
DECODE
SPI_CLK
SPI_CLK
MOSI
MISO
MOSI
MISO
CS
CS
NCN6001 Sends Bit
from READ_REG
MPU Enables Clock
MPU Sends Bit
MPU Enables
Figure 12. Chip Address Decoding Protocol and MISO Sequence
MPU Asserts Chip Set
MPU Asserts Chip Select
MISO Line = High Impedance
Clock
Figure 11. Basic SPI Timings and Protocol
B7
MSB
ADDRESS
B6
CHIP
NCN6804 Reads Bit
MPU Reads Bit
http://onsemi.com
B5
NCN6804
18
B4
The Chip Address is decoded on the third clock pulse.
COMMAND AND CONTROL
generated by the NCN6804, using the CLK_SPI and CS
lines to synchronize the bits carried out by the data byte. The
basic timings are given in Figure 11 and 12. The system runs
with two internal registers associated with MOSI and MISO
data:
WRT_REG is a write only register dedicated to the
MOSI data.
READ_REG is a read only register dedicated to the
MISO data.
internal logic identifies the chip address on the fly (reading
and decoding the three first bits) and validate the right data
present on the line. Consequently, the data format is MSB
first to read the first three signal as bits b5, b6 and b7. The
chip address is decoded from this logic value and validates
the chip according to the S1 pin conditions: see Figure 12.
The MISO signal is activated and data transferred
To accommodate the simultaneous MISO transmit, an
B3
B2
B1
B0
LSB
tclr