isd-t360sb ETC-unknow, isd-t360sb Datasheet - Page 11

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isd-t360sb

Manufacturer Part Number
isd-t360sb
Description
Manufacturer
ETC-unknow
Datasheet
1—HARDWARE
1.2
This section provides details of the functional char-
acteristics of the VoiceDSP processor. It is divided
into the following sections:
1.2.1
The RESET pin is used to reset the VoiceDSP proces-
sor.
On application of power, RESET must be held low
for at least t
all on-chip voltages are completely stable before
operation. Whenever RESET is applied, it must also
remain active for not less than t
and Table 1-10. During this period, and for 100 ms
after, the TST signal, which is an internal signal,
must be high. This can be done with a pull-up re-
sistor on the TST pin.
The value of MWRDY is undefined during the reset
period, and for 100 ms after. The microcontroller
should either wait before polling the signal for the
first time, or the signal should be pulled high dur-
ing this period.
Upon reset, the ENV0 signal is sampled to deter-
mine the operating environment. During reset, the
EMCS/ENV0 pin is used for the ENV0 input signals.
An internal pull-up resistor sets ENV0 to 1.
After reset, the same pin is used for EMCS.
System Load on ENV0
For any load on the ENV0 pin, the voltage should
not drop below V
ISD
Resetting
Clocking
Power-Down Mode
Power and Grounding
Memory Interface
Codec Interface
DESCRIPTION
RESETTING
pwr
after V
ENVh
CC
(see Table 1-8).
is stable. This ensures that
RST
, see Table 1-9
If the load on the ENV0 pin causes the current to
exceed 10 µA, use an external pull-up resistor to
keep the pin at 1.
Figure 1-2 shows a recommended circuit for gen-
erating a reset signal when the power is turned on.
Figure 1-2: Recommended Power-On Reset
1.2.2
The VoiceDSP processor provides an internal oscil-
lator that interacts with an external clock source
through the X1 and X2/CLKIN pins. Either an exter-
nal single-phase clock signal, or a crystal oscilla-
tor, may be used as the clock source.
External Single-Phase Clock Signal
If an external single-phase clock source is used, it
should be connected to the CLKIN signal as
shown in Figure 1-3, and should conform to the
voltage-level requirements for CLKIN stated in
“ELECTRICAL CHARACTERISTICS” on page 1-16.
NOTE
the CLKIN signal is not 5V tolerant.
CLOCKING
V
CC
Circuit
RESET
ISD-T360
V
V
CC
SS
ISD-T360SB
1-3

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