isd-t360sb ETC-unknow, isd-t360sb Datasheet - Page 26

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isd-t360sb

Manufacturer Part Number
isd-t360sb
Description
Manufacturer
ETC-unknow
Datasheet
ISD-T360SB
1.3.3
Definitions
All timing specifications in this section refer to 0.8 V or 2.0 V on the rising or falling edges of the signals, as
illustrated in Figure 1-16 through Figure 1-22, unless specifically stated otherwise.
Maximum times assume capacitive loading of 50pF. CLKIN crystal frequency is 4.096 MHz.
NOTE
NOTE:
NOTE:
1-18
CTTL is an internal signal and is used as a reference to explain the timing of other signals. See
Figure 1-31.
Signal valid, active or inactive time, after a rising edge of CTTL or MWCLK.
Signal valid time, after a falling edge of MWCLK.
SWITCHING CHARACTERISTICS
MWCLK
MWCLK
Figure 1-16: Synchronous Output Signals (Valid, Active and Inactive)
CTTL or
Signal
Signal
Figure 1-17: Synchronous Output Signals (Valid)
0.8V
t
Signal
2.0V
t
Signal
2.0V
0.8V
2.0V
0.8V
Voice Solutions in Silicon™
1—HARDWARE

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