psf2115 ETC-unknow, psf2115 Datasheet - Page 158

• Manufacturer Part Number: psf2115
• Description: Isdn Adapter Circuit Ipac
• Manufacturer: ETC-unknow

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3.2
After reset the CPU has to write a minimum set of registers and an optionally set
dependent on the required features and operating modes.
The CPU may switch the IPAC between power-up and power-down mode, which has no
influence upon the contents of the registers, i.e. the internal state remains stored.
In power-down mode however, all internal clocks are disabled, no interrupts are
forwarded to the CPU.
This state can be used as standby mode, when the IPAC is temporarily not used, thus
minimizing the power consumption.
The individual operating mode must be defined writing the individual MODE register
(MODE, MODEB and MODED).
The need for programming further registers depends on the selected features (operating
mode, address mode, user demands) according to the following tables:
B-Channel registers
Clock Mode
5 (Time Slot Mode)
Note: The clock mode 5 is well known from the HSCX-TE PSB 21525, other clock modes
Table 20 Register Setup
Operating
Mode
Non Auto
Semiconductor Group
are not supported.
Initialization
Address
Mode
Register
CCR2, TSAR, TSAX, XCCR, RCCR
2 Byte
Address Field
(MODEB: ADM = 1)
RAH1
RAH2
RAL1
RAL2
RAH1
RAH2
158
1 Byte
Address Field
(MODEB: ADM = 0)
RAH1 set to 00
RAH2 set to 00
RAL1
RAL2
–
Operational Description
H
H
PSB 2115
PSF 2115
11.97