psf2115 ETC-unknow, psf2115 Datasheet - Page 277

• Manufacturer Part Number: psf2115
• Description: Isdn Adapter Circuit Ipac
• Manufacturer: ETC-unknow

Semiconductor Group
FBS ... FSC/BCL Output Select (LT-S and LT-T modes)
0: FSC is output on AUX3, which is derived from the DCL input by division of 192.
1: BCL single bit clock is output on AUX3. It is derived from the DCL input by division of 2.
Note: SCLK output provides 1.536 MHz in LT-T mode. This may be used for the DCL
CSL2-0 ... IOM-2 Channel Selection for PCM (LT-S and LT-T modes)
Selects one of eight IOM channels to which the PCM interface is connected to.
000: channel 0
001: channel 1
111: channel 7
Note: These bits are ignored in TE mode.
4.4.12
Value after reset: 00
SCFG
PRI ... Priority for D-channel Handler (only in LT-S mode in intelligent NT)
Determines the priority of D-channel access on IOM-2 for the D-channel controller on the
IPAC and for external D-channel sources connected to the IOM-2 interface. The state
machine for D-channel handling controls the S/G bit according to the setting of PRI and
enables the access of internal or external D-channel sources.
0: Priority = 8
1: Priority = 10
Note: The read back value of PRI only contains the programmed value as soon as the
TXD ... S-transmitter Disable
The transmitter of the S-transceiver can be disabled by setting TXD to “1“. This can be
used to reduce power consumption (see chapter 2.5.4).
:
input. This bit is ignored in TE mode.
state machine has switched to the selected priority.
The D-channel handler can be enabled/disabled via bit CONF:IDH.
:
SCFG - SDS Configuration Register (Read/Write)
7
PRI
TXD
H
TLEN
277
TSLT
Detailed Register Description
0
PSB 2115
PSF 2115
11.97
(CB)