psf2115 ETC-unknow, psf2115 Datasheet - Page 182

• Manufacturer Part Number: psf2115
• Description: Isdn Adapter Circuit Ipac
• Manufacturer: ETC-unknow

RFIFOB Contents
(No. of bytes)
1, 2, 3
4 - 7
8 - 15
16 - 31
32 - 64
Note: All available status informations after RME are summarized in table 11.
After the DMA controller has been set up for the reception of the next frame, the CPU
must be issue a RMC command to acknowledge the completion of the receive frame
processing.
The IPAC will not initiate further DMA cycles by activating the DRQRA/B line prior to the
reception of RMC.
Note: It’s also possible to set up the DMA controller immediately after the start of a frame
The following figure gives an example of a DMA controlled reception sequence,
supposed that a long frame (132 bytes) followed by one short frame (12 bytes) is
received.
Figure 86
Semiconductor Group
Serial
Interface
IPAC
CPU
Interface
has been detected using the IPAC’s RFS (Receive Frame Start) interrupt option.
DMA Driven Reception Sequence Example
Receive 132 Bytes
64
DRQR(64)
RD
DMA Request
(No. of Bytes)
4
8
16
32
64
64
136 DMA Read Cycles
DRQR(64)
4
12 Bytes
RD
Receive
12
DRQR(8)
182
RD
RME
Count
(133)
RD
RMC
DRQR(16)
Operational Description
RD
RME
Count
(13)
RD
PSB 2115
PSF 2115
RMC
ITD09653
11.97