psf2115 ETC-unknow, psf2115 Datasheet - Page 90

• Manufacturer Part Number: psf2115
• Description: Isdn Adapter Circuit Ipac
• Manufacturer: ETC-unknow

Semiconductor Group
2.5.5
LT-S
In LT-S mode, the 192-kHz transmit bit clock is synchronized to the IOM clock. In the
receive direction two cases have to be distinguished depending on whether a bus or a
point-to-point operation is programmed in MON-8 Configuration Register (see figure
32):
– In a bus configuration (C/W/P=0), the 192-kHz receive bit clock is identical to the
– In a point-to-point or extended passive bus configuration (C/W/P=1), the 192-kHz
Figure 32
transmit bit clock, shifted by 4.6 s with respect to the transmit edge. According to
CCITT I.430, the receive frame is shifted by two bits with respect to the transmit frame.
receive bit clock is recovered from the receive data stream on the S interface.
According to CCITT I.430, the receive frame can be shifted by 2-8 bits with respect to
the transmit frame at the LT-S. However, note that other shifts are also allowed by the
IPAC (including 0).
Timing Recovery
Clock System of the IPAC in LT-S Mode
MP:
PP:
Receive clock for bus configuration
Receive clock for point-to-point configuration
LT-S Mode
PLL
PLL
90
MP
PP
ITS09633
Functional Description
DCL
FSC
PSB 2115
PSF 2115
11.97