psf2115 ETC-unknow, psf2115 Datasheet - Page 294

• Manufacturer Part Number: psf2115
• Description: Isdn Adapter Circuit Ipac
• Manufacturer: ETC-unknow

LT-T
LT-S
A phase tracking with respect to "S" is performed once in 250 s. As a consequence of
this DPLL tracking, the "high" state of the 1536-kHz clock may be either reduced or
extended by half of one 7.68-MHz period (duty ratio 4:5 or 5:4 instead of 5:5) once every
250 s. Since the other signals are derived from this clock (TE mode), the "high" or "low"
states may likewise be reduced or extended by the same amount once every 250 s.
The phase relationships of the clocks are shown in figure 115.
Clock Timing
The clocks in the different operating modes are summarized in table below with the
respective duty ratios.
Application
TE
Note: M0 and M1 denote the pins MODE0 and MODE1/EAW, respectively.
The 1536-kHz clock (TE mode) is phase-locked to the receive S signal, and derived
using the internal DPLL and the 7.68 MHz
Figure 115
Semiconductor Group
7.68 MHz
1536 kHz *
768 kHz
In TE mode MODE 1 is don’t care (used as EAW pin).
All output clocks are synchronous to the S-receiver.
BCL/SCLK output in LT-S mode is derived from the DCL input clock.
Phase Relationships of IPAC Clock Signals
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
M0 M1
0 X
1 1
1 0
DCL
o: 1536 kHz
1:1
i: 4096 kHz
(max.)
i: 4096 kHz
(max.)
294
o: 8kHz
1:2
i: 8 kHz
i: 8 kHz
FSC
100 ppm crystal.
BCL / SCLK
o: 768 kHz
1:1
o: 1536 kHz
1:1
o: DCL/2
Electrical Characteristics
PSB 2115
PSF 2115
ITD09664
11.97