psf21911 ETC-unknow, psf21911 Datasheet - Page 17
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psf21911
Manufacturer Part Number
psf21911
Description
Isdn Echocancellation Circuit Terminal Applications Iec-q
Manufacturer
ETC-unknow
Datasheet
1.PSF21911.pdf
(164 pages)
- Current page: 17 of 164
- Download datasheet (2Mb)
Semiconductor Group
Pin No.
P-LCC-44 T-QFP64
40
19
37
21
22
1
36
60
38
39
Symbol
Stand-
alone
PCWR
INT
DISS
PS1
PS2
µP
mode
D4
AD4
not used I
INT
MCLK
PS1
PS2
I/O
O
I/O
I/O
I
O
O
O
I
I
17
Function
Power Controller Bus Write Request
Low active.
Data Bus Pin
(Demultiplexed modes)
Address/Data Bus Pin
(Multiplexed mode)
(Serial mode) tie to GND.
Interrupt
Change-sensitive. After a change of
level has been detected the C/I code
“INT” will be issued on IOM. Tie to
GND if not used.
Interrupt Line
(Multiplexed, demultiplexed and serial
modes): Low active.
Disable Power Supply
This pin is set to ’1’ after receipt of
MON-0 LBBD in EOC auto-mode.
Microprocessor Clock Output
(Multiplexed, demultiplexed and serial
modes): provided with four
programmable clock rates: 7.68 MHz,
3.84 MHz, 1.92 MHz and 0.96 MHz.
Power Status 1 (primary).
’1’ indicates primary power supply ok.
The pin level is identical to the
overhead bit ’PS1’ value.
Power Status 2 (secondary)
’1’ indicates secondary power supply
ok. The pin level is identical to the
overhead bit ’PS2’ value.
Pin Definitions and Functions
PSB 21911
PSF 21911
11.97
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