psf21911 ETC-unknow, psf21911 Datasheet - Page 39

• Manufacturer Part Number: psf21911
• Description: Isdn Echocancellation Circuit Terminal Applications Iec-q
• Manufacturer: ETC-unknow

2.4
The parallel/serial microprocessor interface can be selected to be either of the
1. Siemens/Intel non-multiplexed bus type with control signals CS, WR, RD
2. Motorola type with control signals CS, R/W, DS
3. Siemens/Intel multiplexed address/data bus type with control
4. Serial mode using control signals CDIN, CDOUT, CCLK and CS.
The selection is performed via pins ALE/CCLK and SMODE as follows:
Table 5
Siemens/Intel non-Mux
Motorola
Siemens/Intel Mux
Serial
The occurrence of an edge on ALE/CCLK, either positive or negative, at any time during
the operation immediately selects interface type 3 or 4. A return to one of the other
interface types is possible only if a hardware reset is issued.
2.4.1
The microprocessor clock is provided in µP mode on the MCLK-output. Four clock rates
are provided by a programmable prescaler. These are 7.68 MHz, 3.84 MHz, 1.92 MHz
and 0.96 MHz. Switching between the clock rates is realized without spikes. The
oscillator remains active all the time. The clock is synchronized to the 15.36 MHz clock
at the XIN pin.
2.4.2
The watchdog is enabled by setting the SWST:WT bit to “1”. The value of SWST:WT
after hardware reset (pin RES low and pin TSP low) is "0".
After the microcontroller has enabled the watchdog timer it has to write the bit patterns
“10” and “01” in ADF:WTC1 and ADF:WTC2 within a period of 132 ms. If it fails to do so,
a reset signal of 5 ms at pin RST is generated. The clock at pin MCLK remains active
during this reset.
Semiconductor Group
signals CS, WR, RD, ALE
Microprocessor Interface Modes
Microprocessor Interface
Microprocessor Clock Output
Watchdog Timer
edge
ALE
0
1
edge
1
SMODE
x
x
0
39
Microprocessor Interface
PSB 21911
PSF 21911
11.97