tda6651tt/c3/s3 NXP Semiconductors, tda6651tt/c3/s3 Datasheet - Page 8

• Manufacturer Part Number: tda6651tt/c3/s3
• Description: 5 V Mixer/oscillator And Low Noise Pll Synthesizer For Hybrid Terrestrial Tuner Digital And Analog
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. I
TDA6650TT_6651TT_5
Product data sheet
2
C-bus protocol
8.1 Write mode; R/W = 0
Linked to this noise improvement, some disturbances may become visible while they were
not visible because they were hidden into the noise in analog dedicated applications and
circuits.
This is especially true for disturbances coming from the I
is intended for the MOPLL or for another slave on the bus.
To avoid this I
to use a bus gate that enables the signal on the bus to drive the MOPLL only when the
communication is intended for the tuner part (such a kind of I
the NXP terrestrial channel decoders), and to avoid unnecessary repeated sending of the
same information.
The TDA6650TT; TDA6651TT is controlled via the two-wire I
there is one device address (7 bits) and the R/W bit for selecting read or write mode. To be
able to have more than one MOPLL in an I
is selected depending on the voltage applied to address selection pin AS (see
The TDA6650TT; TDA6651TT fulfils the fast mode I
specification, except for the timing as described in
designed in such a way that the pins SCL and SDA can be connected to 5 V, 3.3 V
or to 2.5 V pulled-up I
Table
After the address transmission (first byte), data bytes can be sent to the device (see
Table
I
within one single transmission (address + 5 data bytes).
The TDA6650TT; TDA6651TT can also be partly programmed on the condition that the
first data byte following the address is byte 2 (divider byte 1) or byte 4 (control byte 1). The
first bit of the first data byte transmitted indicates whether byte 2 (first bit = 0) or byte 4
(first bit = 1) will follow. Until an I
data bytes can be entered without the need to re-address the device. The fractional
calculator is updated only at the end of the transmission (STOP condition). Each control
byte is loaded after the 8th clock pulse of the corresponding control byte. Main divider
data are valid only if no new I
computation period of 50 s.
Both DB1 and DB2 need to be sent to change the main divider ratio. If the value of the
ratio selection bits R2, R1 and R0 are changed, the bytes DB1 and DB2 have to be sent in
the same transmission.
2
C-bus transceiver has an auto-increment facility that permits programming the device
5).
6). Five data bytes are needed to fully program the TDA6650TT; TDA6651TT. The
2
C-bus crosstalk and be able to have a clean noise spectrum, it is necessary
2
Rev. 05 — 10 January 2007
C-bus lines, depending on the voltage applied to pin BVS (see
2
C-bus transmission is started (START condition) during the
2
C-bus STOP condition is sent by the controller, additional
5 V mixer/oscillator and low noise PLL synthesizer
TDA6650TT; TDA6651TT
2
C-bus system, one of four possible addresses
Figure
2
C-bus, according to the NXP I
2
C-bus traffic, whatever this traffic
4. The I
2
2
C-bus. For programming,
C-bus gate is included into
2
C-bus interface is
© NXP B.V. 2007. All rights reserved.
Table
2
C-bus
8 of 54
8).