w25q80bv Winbond Electronics Corp America, w25q80bv Datasheet - Page 38

• Manufacturer Part Number: w25q80bv
• Description: 8m-bit Serial Flash Memory With Dual And Quad Spi
• Manufacturer: Winbond Electronics Corp America

10.2.19 Continuous Read Mode Bits (M7-0)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad
I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random
Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place)
to be performed on serial flash devices.
M7-0 need to be set by the Dual/Quad I/O Read instructions. M5-4 are used to control whether the 8-bit
SPI instruction code (BBh, EBh, E7h or E3h) is needed or not for the next command. When M5-4 = (1,0),
the next command will be treated same as the current Dual/Quad I/O Read command without needing
the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all
commands can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be
used.
10.2.20 Continuous Read Mode Reset (FFh or FFFFh)
Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the
Continuous Read Mode and return to normal SPI operation, as shown in figure 18.
Since W25Q80BV does not have a hardware Reset pin, so if the controller resets while W25Q80BV is set
to Continuous Mode Read, the W25Q80BV will not recognize any initial standard SPI instructions from
the controller. To address this possibility, it is recommended to issue a Continuous Read Mode Reset
instruction as the first instruction after a system Reset. Doing so will release the device from the
Continuous Read Mode and allow Standard SPI instructions to be recognized.
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The
instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are
needed to shift in instruction “FFFFh”.
/CS
/CS
CLK
CLK
IO
IO
IO
IO
IO
IO
IO
IO
0
0
1
1
2
2
3
3
Mode 3
Mode 3
Mode 0
Mode 0
Figure 18. Continuous Read Mode Reset for Fast Read Dual/Quad I/O
0
0 0
1
1 1
Mode Bit Reset
Mode Bit Reset
for Quad I/O
for Quad I/O
2
2 2
3
3 3
FFh
FFh
4
4 4
5
5 5
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6
6 6
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
7
7 7
8
8 8
9
9 9
10
10
10
11
11
11
FFh
FFh
12
12
12
Mode Bit Reset
Mode Bit Reset
for Dual I/O
for Dual I/O
13
13
13
14
14
14
W25Q80BV
15
15
15
Mode 3
Mode 3
Mode 0
Mode 0