m58lt256jsb STMicroelectronics, m58lt256jsb Datasheet - Page 107

• Manufacturer Part Number: m58lt256jsb
• Description: 256 Mbit 16 Mb 16, Multiple Bank, Multilevel, Burst 1.8 V Supply, Secure Flash Memories
• Manufacturer: STMicroelectronics

M58LT256JST, M58LT256JSB
15
Revision history
Table 49.
18-Dec-2006
23-Feb-2007
31-Oct-2006
27-Jun-2007
01-Oct-2007
18-Jul-2006
Date
Document revision history
Revision
0.1
0.2
0.3
1
2
3
Initial release.
Description of CR2-CR0 011 value modified in
Configuration Register
Table 12: Burst type definition
Timings modified in
cycles,.
V
ratings.
Values changed in
V
Figure 24: Erase suspend and resume flowchart and pseudocode
modified.
Appendix D: Command interface state tables
Document status promoted from Target Specification to Preliminary
Data. Small text changes.
Output Enable modified.
Section 6.9: Burst length bits (CR2-CR0)
Device architecture corrected (see
Figure 3: Memory map
I
characteristics -
suspend AC waveforms
values modified under
power-up AC
Synchronous burst read AC
burst read suspend AC waveforms
AC
read AC
Appendix B: Common Flash interface
Block Lock Down confirm (2Fh) removed from
interface states - lock table, next state
interface states - lock table, next output
Document status promoted from Preliminary Data to full Datasheet.
Section 7.2: Synchronous burst read mode
16 word boundary (wrap) feature removed from the document.
Two packing options added in
scheme.
Small text changes.
Changed deassertion condition in
read mode
is valid. Changed T
Absolute maximum ratings
DD1
IO
PP1
characteristics. t
max and V
and I
modified in
characteristics.
DD6
to state that WAIT is only de-asserted when output data
characteristics). t
parameter values updated in
DDQ
currents.
Table 21: DC characteristics -
Table 20: DC characteristics -
A
max modified in
ELTV
Table 16: Program/erase times and endurance
and T
Other conditions
and Note 2 added.
and
modified. t
Section 5.4: Program status bit (SR4)
timing modified in
Figure 13: Synchronous burst read
Wait (WAIT)
BIAS
from -25 to -40.
Appendix A: Block address
waveforms,
Changes
modified.
Table 28: Ordering information
ELTV
minimum values in
Section 7.2: Synchronous burst
PLWL
Table 2: Bank
and
timing removed from
Table 17: Absolute maximum
modified.
and
signal behavior in relation to
, t
Table 23: Synchronous read
(see
state. Small text changes.
Figure 13: Synchronous
modified.
PLEL
Table 48: Command
Table 22: Asynchronous
Table 20: DC
modified.
Table 26: Reset and
modified.
, t
Table 47: Command
Table 11:
voltages.
PLGL
currents.
architecture,
Revision history
Table 17:
and t
tables).
Figure 11:
PLLL
107/108
and