m58lt256jsb STMicroelectronics, m58lt256jsb Datasheet - Page 24

• Manufacturer Part Number: m58lt256jsb
• Description: 256 Mbit 16 Mb 16, Multiple Bank, Multilevel, Burst 1.8 V Supply, Secure Flash Memories
• Manufacturer: STMicroelectronics

Command interface
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Buffer Program command
The Buffer Program command uses the device’s 32-word write buffer to speed up
programming. Up to 32 words can be loaded into the write buffer. The Buffer Program
command dramatically reduces in-system programming time compared to the standard non-
buffered program command.
Four successive steps are required to issue the Buffer Program command.
1.
After the first bus write cycle, read operations in the bank output the contents of the Status
Register. Status Register bit SR7 should be read to check that the buffer is available
(SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to
update the Status Register contents.
2.
3.
4.
All the addresses used in the buffer program operation must lie within the same block.
Invalid address combinations or failing to follow the correct sequence of bus write cycles
sets an error in the Status Register and aborts the operation without affecting the data in the
memory array.
If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not
accepted. Clear the Status Register before re-issuing the command.
If the block being programmed is protected, an error is set in the Status Register and the
operation aborts without affecting the data in the memory array.
During buffer program operations the bank being programmed only accepts the Read Array,
Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase
Suspend commands, and all other commands are ignored.
Refer to
not being programmed.
See
flowchart on using the Buffer Program command.
Appendix
The first bus write cycle sets up the Buffer Program command. The setup code can be
addressed to any location within the targeted block.
The second bus write cycle sets up the number of words to be programmed. Value n is
written to the same block address, where n+1 is the number of words to be
programmed.
Use n+1 bus write cycles to load the address and data for each word into the write
buffer. Addresses must lie within the range from the start address to the start address
+ n, where the start address is the location of the first data to be programmed.
Optimum performance is obtained when the start address corresponds to a 32-word
boundary.
The final bus write cycle confirms the Buffer Program command and starts the program
operation.
Section 8
C,
Figure 21: Buffer program flowchart and pseudocode
for detailed information about simultaneous operations allowed in banks
M58LT256JST, M58LT256JSB
for a suggested