cy14b101l Cypress Semiconductor Corporation., cy14b101l Datasheet - Page 3

• Manufacturer Part Number: cy14b101l
• Description: 1-mbit 128k X 8 Nvsram
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-06400 Rev. *D
Pin Definitions
Device Operation
The CY14B101L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY14B101L supports infinite reads and
writes just like a typical SRAM. In addition, it provides infinite
RECALL operations from the nonvolatile cells and up to
200,000 STORE operations.
SRAM Read
The CY14B101L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A
be accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of t
cycle #1). If the READ is initiated by CE or OE, the outputs will
be valid at t
The data outputs will repeatedly respond to address changes
within the t
any control input pins, and will remain valid until another
address change or until CE or OE is brought high, or WE or
HSB is brought low.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle.
Pin Name
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
A
V
HSB
0
V
V
WE
CE
OE
NC
–A
CAP
SS
CC
16
0-16
AA
ACE
Power Supply Power Supply inputs to the device.
Power Supply Autostore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
No Connect No Connect. This pin is not connected to the die.
determines which of the 131,072 data bytes will
access time without the need for transitions on
I/O Type
or at t
Ground
Input
Input
Input
Input
DOE
, whichever is later (READ cycle #2).
Address Inputs used to select one of the 131,072 bytes of the nvSRAM.
Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE high causes the I/O pins to tri-state.
Ground for the device. Should be connected to ground of the system.
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor
keeps this pin HIGH if not connected. (Connection Optional)
nonvolatile elements.
PRELIMINARY
AA
(READ
The data on the common I/O pins I/O
memory if it is valid t
WRITE or before the end of an CE controlled WRITE. It is
recommended that OE be kept high during the entire WRITE
cycle to avoid data bus contention on common I/O lines. If OE
is left low, internal circuitry will turn off the output buffers t
after WE goes low.
AutoStore™ Operation
The CY14B101L stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store, activated by HSB, Software Store, activated by an
address sequence, and AutoStore, on device power-down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B101L.
During normal operation, the device will draw current from V
to charge a capacitor connected to the V
charge will be used by the chip to perform a single STORE
operation. If the voltage on the V
the part will automatically disconnect the V
A STORE operation will be initiated with power provided by the
V
Figure 1 shows the proper connection of the storage capacitor
(V
teristics table for the size of V
is driven to 5V by a charge pump internal to the chip. A pull-up
should be placed on WE to hold it inactive during power-up.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. The HSB signal can be monitored by the system
to detect an AutoStore cycle is in progress.
CAP
CAP
Description
capacitor.
) for automatic store operation. Refer to the DC Charac-
SD
before the end of a WE controlled
CAP
CC
. The voltage on the V
pin drops below V
0–7
will be written into the
CY14B101L
CAP
CAP
pin. This stored
pin from V
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SWITCH
CAP
HZWE
CC
pin
CC
[+] Feedback
,
.