cy14b101l Cypress Semiconductor Corporation., cy14b101l Datasheet - Page 4

• Manufacturer Part Number: cy14b101l
• Description: 1-mbit 128k X 8 Nvsram
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 001-06400 Rev. *D
Hardware STORE (HSB) Operation
The CY14B101L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin
is driven low, the CY14B101L will conditionally initiate a
STORE operation after t
only begin if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14B101L will continue SRAM operations for
t
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, t
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
During any STORE operation, regardless of how it was
initiated, the CY14B101L will continue to drive the HSB pin
low, releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14B101L will
remain disabled until the HSB pin returns high.
If HSB is not used, it should be left unconnected.
Hardware RECALL (Power-up)
During power-up, or after any low-power condition (V
V
V
RECALL cycle will automatically be initiated and will take
t
DELAY
HRECALL
SWITCH
CC
once again exceeds the sense voltage of V
. During t
), an internal RECALL request will be latched. When
to complete.
DELAY
Figure 1. AutoStore
V
CAP
, multiple SRAM READ operations may
DELAY
DELAY
. An actual STORE cycle will
, to complete. However, any
TM
V
WE
Mode
CC
SWITCH
PRELIMINARY
V
CC
, a
CC
<
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The CY14B101L
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence, or the
sequence will be aborted and no STORE or RECALL will take
place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
The software sequence may be clocked with CE controlled
READs or OE controlled READs. Once the sixth address in the
sequence has been entered, the STORE cycle will commence
and the chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence, although it is
not necessary that OE be low for the sequence to be valid.
After the t
again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE controlled READ
operations must be performed:
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the t
the SRAM will once again be ready for READ and WRITE
operations. The RECALL operation in no way alters the data
in the nonvolatile elements.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
STORE
cycle time has been fulfilled, the SRAM will
CY14B101L
RECALL
Page 4 of 19
cycle time
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