hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 12

• Manufacturer Part Number: hyb18m1g16
• Description: Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
• Manufacturer: Qimonda

2.2.1.2
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in
2.2.1.3
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered and the latency is 3 clocks, the first data element will be valid after (2 *
command is registered and the latency is 2 clocks, the first data element will be valid after (
to the READ command description.
Rev.1.0, 2007-03
10242006-Y557-TZXW
Burst Type
Read Latency
Table
5.
12
t
CK
+
HY[B/E]18M1G16[0/1]BF
t
1-Gbit DDR Mobile-RAM
AC
). For details please refer
t
CK
+
t
AC
Data Sheet
). If a READ