hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 59

• Manufacturer Part Number: hyb18m1g16
• Description: Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
• Manufacturer: Qimonda

1) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for -7.5 speed grade.
2) Input slew rate is 1.0 V/ns.
3) Definitions for IDD:
4) All parameters are measured with no output loads.
5) Assuming one of the die is in active RD/WR, whereas the other is in X/Y/Z mode, where X is active non Power-Down standby, Y is
6)
Rev.1.0, 2007-03
10242006-Y557-TZXW
Parameter & Test Conditions
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH,
control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH,
control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH, CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are
STABLE
Operating burst read current:
one bank active; BL = 4; CL = 3;
IOUT = 0 mA; address input are SWITCHING; 50% data change each
burst transfer
Operating burst write current:
one bank active; BL = 4;
address inputs are SWITCHING; 50% data change each burst transfer
Auto-Refresh current:
t
control inputs are SWITCHING; data bus inputs are STABLE
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are
STABLE; data bus inputs are STABLE
Deep Power Down current
RC
LOW is defined as VIN ≤ 0.1 *
HIGH is defined as VIN ≥ 0.9 *
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- address and command: inputs changing between HIGH and LOW once per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE
precharge non Power-Down standby, and Z is active Power-Down standby. Note, X/Y scenarios apply to 1CKE or 2CKE options; whereas
Z is only applicable for 2CKE option.
I
=
DD8
t
RFCmin
value shown as typical.
;
t
CK
=
t
CKmin
; burst refresh; CKE is HIGH; address and
t
CK
=
V
t
V
CKmin
DDQ
DDQ
t
CK
;
;
; continuous write bursts;
=
t
CKmin
; continuous read bursts;
t
t
CK
CK
=
=
t
t
CKmin
CKmin
; address and
; address and
59
Symbol
I
I
I
I
I
I
I
I
I
DD3P
DD3PS
DD3N
DD3NS
DD4R
DD4W
DD5
DD6
DD8
4
3.0
50
5.0
130/125/110 100/90/80 mA
135/130/115 100/90/80 mA
370
see
Table 27
50
6)
Values
- 6
HY[B/E]18M1G16[0/1]BF
4
3.0
44
5.0
270
see
Table 27
1-Gbit DDR Mobile-RAM
Values
- 7.5
mA
mA
mA
mA
mA
µA
µA
Unit Note
Data Sheet
3)4)
5)
5)
1)2)