s-24cs64a Seiko Instruments Inc., s-24cs64a Datasheet - Page 12

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s-24cs64a

Manufacturer Part Number
s-24cs64a
Description
2-wire Cmos Serial E2prom
Manufacturer
Seiko Instruments Inc.
Datasheet

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12
2-WIRE CMOS SERIAL E
S-24CS64A
5. Device Addressing
6. Write
6.1 Byte Write
SDA LINE
To start communication, the master device on the system generates a start condition to the bus line. Next,
the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus.
The 4 most significant bits of the device address are called the “Device Code”, and are fixed to “1010”.
Successive 3 bits are called the “Slave Address”. These 3 bits are used to identify a device on the system
bus and are compared with the predetermined value which is defined by the address input pins (A0, A1
and A2). When the comparison result matches, the slave device responds with an acknowledge during the
9th clock cycle.
When the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following
a start condition, the E
address and responds with an acknowledge. And the E
address and responds with an acknowledge. After the E
with an acknowledge, it receives a stop condition and that initiates the write cycle at the addressed
memory.
During the write cycle all operations are forbidden and no acknowledge is generated.
S
T
A
R
T
M
S
B
1
0
ADDRESS
1
DEVICE
0
A2 A1 A0
MSB
2
1
PROM acknowledges it. The E
L
S
B
W
W
R
2
R
T
E
0
/
I
PROM
Device Code
C
A
K
0
UPPER WORD ADDRESS
X
X
Figure 11 Device Address
X
1
W12W11W10W9 W8
Figure 12 Byte Write
Seiko Instruments Inc.
0
C
A
K
A2
LOWER WORD ADDRESS
W7 W6 W5 W4 W3 W2 W1 W0
Slave Address
2
PROM then receives the upper 8 bits of the word
2
2
A1
PROM receives 8-bit write data and responds
PROM receives the lower 8 bits of the word
A0
R / W
C
A
K
A
C
K
LSB
D7 D6 D5 D4 D3 D2 D1 D0
(ADDRESS INCREMENT)
DATA
ADR INC
Rev.4.1
C
A
K
S
T
O
P
_00

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