s-24cs64a Seiko Instruments Inc., s-24cs64a Datasheet - Page 16

• Manufacturer Part Number: s-24cs64a
• Description: 2-wire Cmos Serial E2prom
• Manufacturer: Seiko Instruments Inc.

16
LINE
SDA
2-WIRE CMOS SERIAL E
S-24CS64A
7.2 Random Read
S
T
A
R
T
Random read is used to read the data at an arbitrary memory address.
A dummy write is performed to load the memory address into the address counter.
When the E
following a start condition, it responds with an acknowledge. The E
word address and responds with an acknowledge. Next the E
address and responds with an acknowledge. The memory address is loaded to the address counter in the
E
of write data follows in a byte write and in a page write.
Since the memory address is loaded into the memory address counter by dummy write, the master device
can read the data starting from the arbitrary memory address by transmitting a new start condition and
performing the same operation in the current address read.
That is, when the E
“1”, following a start condition signal, it responds with an acknowledge. Next, 8-bit data is transmitted
from the E
acknowledge, the reading of E
2
M
S
B
PROM by these operations. Reception of write data does not follow in a dummy write whereas reception
1 0 1 0
ADDRESS
DEVICE
A2 A1 A0
2
2
PROM in synchronous to the SCL clock. The master device outputs stop condition not an
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “0”
S
B
L
W
W
R
R
E
T
0
/
I
A
C
K
2
PROM receives a 7-bit device address and a 1-bit read / write instruction code set to
UPPER WORD ADDRESS
X
X X
DUMMY WRITE
X
2
W12 W11 W10
PROM
2
PROM is ended.
W9 W8
Figure 16 Random Read
A
C
K
LOWER WORD ADDRESS
W7 W6 W5 W4 W3 W2 W1
Seiko Instruments Inc.
W
A
C
K
S
T
A
R
T
2
M
S
B
1 0 1 0
PROM then receives an 8-bit lower word
ADDRESS
DEVICE
2
PROM then receives an 8-bit upper
A2 A1 A0
S
B
L
W
R
R
D
E
A
1
/
C
A
K
D7 D6 D5 D4 D3 D2 D1 D0
下図へ続く
NO ACK from
Master Device
DATA
Rev.4.1
ADR INC
_00
S
T
O
P