s-24cs64a Seiko Instruments Inc., s-24cs64a Datasheet - Page 25

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s-24cs64a

Manufacturer Part Number
s-24cs64a
Description
2-wire Cmos Serial E2prom
Manufacturer
Seiko Instruments Inc.
Datasheet

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Rev.4.1
6. Data hold time (t
7. SDA pin and SCL pin noise suppression time
If SCL and SDA of the E
condition from being mistakenly recognized due to the effect of noise. If a start / stop condition is
mistakenly recognized during communication, the E
It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µ s minimum in the S-24CS64A.
This is to prevent time lag caused by the load of the bus line from generating the stop (or start) condition.
The S-24CS64A includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This means
that if the power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed.
The guaranteed for details, refer to noise suppression time (t
_00
Noise suppression time (t
Figure 30 Noise Suppression Time for SDA and SCL Pins
HD. DAT
[ns]
= 0 ns)
SDA
SCL
2
PROM are changed at the same time, it is necessary to prevent the start / stop
I
) Max.
Figure 29 E
Seiko Instruments Inc.
300
200
100
2
PROM Data Hold Time
t
HD. DAT
2
Power supply voltage (V
PROM enters the standby status.
= 0.3 µs Min.
2
I
) in Table 11 .
[V]
3
2-WIRE CMOS SERIAL E
4
CC
)
5
S-24CS64A
2
PROM
25

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