m29dw256g Numonyx, m29dw256g Datasheet - Page 14

• Manufacturer Part Number: m29dw256g
• Description: 256-mbit X16, Multiple Bank, Page, Dual Boot 3 V Supply Flash Memory
• Manufacturer: Numonyx

2.7
2.8
2.9
2.10
2.11
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Reset (RP)
The reset pin can be used to apply a hardware reset to the memory.
A hardware reset is achieved by holding reset Low, V
High, V
t
characteristics,
Ready/busy output (RB)
The ready/busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations ready/busy is
Low, V
mode, auto select mode and erase suspend mode.
After a hardware reset, bus read and bus write operations cannot begin until ready/busy
becomes high-impedance. See
Figure
The use of an open-drain output allows the ready/busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
V
V
The command interface is disabled when the V
voltage, V
during power-up, power-down and power surges. If the program/erase controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1 μF capacitor should be connected between the V
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations (see
I
V
V
independently from V
V
V
which must be connected to the system ground.
RHEL
CC1
CC
CCQ
SS
CC
CCQ
ss
, I
is the reference for all voltage measurements. The device features two V
provides the power supply for all operations (read, program and erase).
, whichever occurs last. See
ground
CC2
provides the power supply to the I/O pins and enables all outputs to be powered
supply voltage
OL
18.
IH
input/output supply voltage
, the memory will be ready for bus read and bus write operations after t
(see
, I
LKO
CC3
. This prevents bus write operations from accidentally damaging the data
Table 16: Status register
Figure 17
in
Table 22: DC
CC
.
and
Figure 18
Table 26: Reset AC
characteristics).
Section 2.8: Ready/busy output
bits). Ready/busy is high-impedance during read
for more details.
CC
supply voltage is less than the lockout
characteristics,
IL
, for at least t
CC
supply voltage pin and the V
(RB),
Figure 17
PLPX
Table 26: Reset AC
. After reset goes
SS
and
pins both of
PHEL
or
SS