m29dw256g Numonyx, m29dw256g Datasheet - Page 61

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m29dw256g

Manufacturer Part Number
m29dw256g
Description
256-mbit X16, Multiple Bank, Page, Dual Boot 3 V Supply Flash Memory
Manufacturer
Numonyx
Datasheet

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Figure 16. Chip enable controlled program waveforms
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see
4. See
Table 25.
1. Only available upon customer request.
Symbol
t
t
t
t
t
t
t
t
t
EHWH
t
DVEH
EHDX
WLEL
ELEH
EHEL
GHEL
AVAV
AVEL
ELAX
of status register data polling bit.
and
Table 23: Read AC characteristics
Table 24: Write AC characteristics, write enable
t
Alt.
t
t
t
t
CPH
t
t
t
t
WC
WH
WS
CP
DS
DH
AS
AH
Write AC characteristics, chip enable controlled
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Chip Enable High to Input transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address transition
Output Enable High Chip Enable Low
DQ0-DQ15
A0-A23
W
G
E
tAVAV
for details on the timings.
tWLEL
tGHEL
Parameter
tDVEH
tELEH
3rd cycle
tAVEL
555h
AOh
controlled,
4th cycle
M29DW_Chip_Enable_Controlled_Program_Waveforms
tEHWH
tEHDX
PA
Table 25: Write AC characteristics, chip enable controlled
tEHEL1
PD
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
tELAX
Section 7.1: Data polling bit
tWHWH1
Data Polling
60 ns
65
35
45
30
45
0
0
0
0
0
PA
DQ7
(1)
M29DW256G
D OUT
70 ns
75
35
45
30
45
0
0
0
0
0
(DQ7)).
80 ns
85
35
45
30
45
0
0
0
0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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