dm9302 Davicom Semiconductor, Inc., dm9302 Datasheet - Page 19

• Manufacturer Part Number: dm9302
• Description: 10/100mbps Ethernet Fiber/twisted Pair Media Converter With Local Bus
• Manufacturer: Davicom Semiconductor, Inc.

6.9 EEPROM & PHY Address Register (0CH)
6.10 EEPROM & PHY Data Registers (0DH~0EH)
6.11 Link Change Control Register (0FH)
6.12 Processor Port Physical Address Registers (10H~15H)
6.13 Processor Port Multicast Address Registers (16H~1DH)
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
Bit
7:6
4:3
1:0
7:0
7:0
Bit
7:6
5:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Bit
Bit
Bit
5
2
3
2
1
0
RESERVED
RESERVED
RESERVED
PHY_ADR
LINKEN
LINKST
EPDRH
ERPRW
EPDRL
ERPRR
Name
EROA
Name
Name
Name
Name
MAB7
MAB6
MAB5
EPOS
ERRE
PAB5
PAB4
PAB3
PAB2
PAB1
PAB0
PH01,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RO
Default
Default
Default
Default
PE0,RW
PH0,RO
E,RW
E,RW
E,RW
E,RW
E,RW
E,RW
X,RW
X,RW
X,RW
Type
0,RO
0,RO
0,RO
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0.
EEPROM Word Address or PHY Register Address
EEPROM or PHY Low Byte Data (0DH)
This data is made to write/read low byte of word address defined in Reg. 0CH to
EEPROM or PHY
EEPROM or PHY High Byte Data (0EH)
This data is made to write/read high byte of word address defined in Reg. 0CH to
EEPROM or PHY
Physical Address Byte 5 (15H)
Physical Address Byte 4 (14H)
Physical Address Byte 3 (13H)
Physical Address Byte 2 (12H)
Physical Address Byte 1 (11H)
Physical Address Byte 0 (10H)
Multicast Address Byte 7 (1DH)
Multicast Address Byte 6 (1CH)
Multicast Address Byte 5 (1BH)
Reserved
Link Change Event Enable
When both set of this bit and bit 6 of NCR, it enables link change status Event
Reserved
Link Change Event Status
When set, it indicates that Link Status Change Event (link of port 0 or 1) occurred
This bit can be cleared by write 1 to bit 5 of NSR or write 0 to bit 6 of NCR.
Reserved
Description
Description
Description
Description
Description
DM9302
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