dm9302 Davicom Semiconductor, Inc., dm9302 Datasheet - Page 40

• Manufacturer Part Number: dm9302
• Description: 10/100mbps Ethernet Fiber/twisted Pair Media Converter With Local Bus
• Manufacturer: Davicom Semiconductor, Inc.

8.3 PHY ID Identifier Register #1 (PHYID1) – 02H
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9302. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
8.4 PHY ID Identifier Register #2 (PHYID2) – 03H
8.5 Auto-negotiation Advertisement Register (ANAR) – 04H
This register contains the advertised abilities of this DM9302 device as they will be transmitted to its link partner
during Auto-negotiation.
40
15-10
15-0
9-4
3-0
Bit
Bit
Bit
15
14
1
0
Jabber detect
VNDR_MDL
MDL_REV
OUI_MSB
Bit Name
Bit Name
Bit Name
OUI_LSB
Extended
capability
ACK
NP
<101110>,
<001011>,
<0181H>
<0000>,
Default
Default
Default
1,RO/P
0,RO/P
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
0, RO
RO/P
RO/P
RO/P
0,RO
the occurrence of a link failure condition causes the link status bit to
be cleared and remain cleared until it is read via the management
interface
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a DM9302 reset. This bit works only in
10Mbps mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
OUI Most Significant Bits
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of
this register respectively. The most significant two bits of the OUI
are ignored (the IEEE standard refers to these as bit 1 and 2)
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Five bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 4)
Next page Indication
1 = Next page available
0 = No next page available
The DM9302 has no next page, so this bit is permanently set to 0
Acknowledge
1 = Link partner ability data reception acknowledged
Description
Description
Description
DM9302
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009