x9525vzi Intersil Corporation, x9525vzi Datasheet - Page 4

• Manufacturer Part Number: x9525vzi
• Description: Dual Dcp, Eeprom Memory
• Manufacturer: Intersil Corporation

minate further data transmissions if an ACKNOWLEDGE
is not detected. The master must then issue a STOP
condition to place the device into a known state.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the X9525
can be split up into three main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed on
each of these individual parts, a 1, 2 or 3 Byte proto-
col is used. All operations however must begin with
the Slave Address Byte being issued on the SDA pin.
The Slave address selects the part of the X9525 to
be addressed, and specifies if a Read or Write opera-
tion is to be performed.
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of four parts:
—The Device Type Identifier which consists of the most
—SA3 is the Physical Device Address bit, whose logic
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9525.
level must match that of the corresponding A
order to enable communication to the X9525.
Data Output
Data Output
Transmitter
Receiver
Master
Master
from
from
from
from
SCL
SCL
4
Start
Figure 3.
Acknowledge Response From Receiver
1
0
pin in
X9525
—The next two bits (SA2 - SA1) are the Internal Device
—The Least Significant Bit of the Slave Address (SA0)
Address bits. Setting these bits to 00 internally selects
the EEPROM array, while setting these bits to 11
selects the DCP structures in the X9525. The CON-
STAT Register may be selected using the Internal
Device Address 10.
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA2 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
Figure 4.
SA7
1 0 1 0
Internal Address
DEVICE TYPE
(SA2 - SA1)
IDENTIFIER
Bit SA0
SA6
8
00
10
11
0
1
SA5
Slave Address Format
Acknowledge
SA4
PHYSICAL
ADDRESS
DEVICE
SA3
Internally Addressed
9
A
CONSTAT Register
0
EEPROM Array
SA2
Operation
INTERNAL
ADDRESS
Device
WRITE
DEVICE
READ
DCP
SA1
READ /
WRITE
R/W
SA0
January 3, 2006
FN8210.1