x9525vzi Intersil Corporation, x9525vzi Datasheet - Page 5

• Manufacturer Part Number: x9525vzi
• Description: Dual Dcp, Eeprom Memory
• Manufacturer: Intersil Corporation

Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9525
initiates an internal high voltage write cycle. This cycle
typically requires 5 ms. During this time, no further Read
or Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy with the high voltage cycle then no ACKNOWL-
EDGE will be returned. If the device has completed the
write operation, an ACKNOWLEDGE will be returned
and the host can then proceed with a read or write opera-
tion. (Refer to Figure 5.).
Figure 5.
command sequence?
Issue Slave Address
Byte (Read or Write)
complete. Continue
Byte load completed
High Voltage Cycle
command sequence
Enter ACK Polling
by issuing STOP.
Continue normal
Issue START
Read or Write
PROCEED
returned?
Acknowledge Polling Sequence
ACK
YES
YES
5
NO
NO
Issue STOP
Issue STOP
X9525
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9525 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
On power-up of the X9525, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The intial values of the
DCP WCR’s (before the contents of the NVM is loaded
into the WCR) are 0 and 255 for DCP1 (100 tap) and
DCP2 (256 tap) respectively. The data in the WCR is
then decoded to select and enable one of the respective
FET switches. A “make before break” sequence is used
internally for the FET switches when the wiper is moved
from one tap position to another.
w
REGISTER
COUNTER
VOLATILE
MEMORY
WIPER
x
(NVM)
(WCR)
NON
Figure 6.
) output. Within each individual array, only one
DECODER
DCP Internal Structure
N
2
1
0
SWITCHES
“WIPER”
FET
RESISTOR
ARRAY
Hx
January 3, 2006
and R
FN8210.1
R
R
R
Hx
Lx
Wx
Lx