tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 105
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tmp86fh46bng
Manufacturer Part Number
tmp86fh46bng
Description
8 Bit Microcontroller Tlcs-870/c Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86FH46BNG.pdf
(216 pages)
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Part Number:
TMP86FH46BNG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Example :Setting the timer mode with source clock fc/2
9.3
9.3.1
Table 9-4 Source Clock for Timer Counter 3, 4 (Internal Clock)
8-bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a
16-bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up coun-
ter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
DV7CK = 0
fc/2
Function
The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO),
NORMAL1/2, IDLE1/2 mode
Note:In the timer mode, do not select a source clock other than those shown above.
(TimerCounter4, fc = 16.0 MHz)
fc/2
fc/2
fc/2
11
ter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter
is cleared. After being cleared, the up-counter restarts counting.
[Hz]
8-Bit Timer Mode (TC3 and 4)
7
5
3
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in
Note 3: j = 3, 4
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-coun-
Source Clock (Note)
the shift register configuration in the timer mode, the new value programmed in TTREGj is in effect imme-
diately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected op-
eration may not be obtained.
DV7CK = 1
fs/2
fc/2
fc/2
fc/2
3
LD
DI
SET
EI
LD
LD
[Hz]
7
5
3
(TTREG4), 0AH
(EIRH). 1
(TC4CR), 00010000B
(TC4CR), 00011000B
SLOW1/2,
SLEEP1/2
fs/2
mode
3
-
-
-
[Hz]
fc = 16 MHz
7
Page 87
Hz and generating an interrupt 80 μs later
128 μs
500 ns
8 μs
2 μs
; Sets the timer register (80 μs ÷ 2
; Enables INTTC4 interrupt.
; Sets the operating clock to fc/2
; Starts TC4.
Resolution
fs = 32.768 kHz
244.14 μs
-
-
-
7
fc = 16 MHz
, and 8-bit timer mode.
7
127.5 μs
32.6 ms
/fc = 0AH).
2.0 ms
510 μs
Maximum Setting Time
TMP86FH46BNG
fs = 32.768 kHz
62.3 ms
-
-
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