tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 51

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example 1 :Enables interrupts individually and sets IMF
Example 2 :C compiler description example
Interrupt Enable Registers
Interrupt Latches
(003BH, 003AH)
(003DH, 003CH)
EIRH,EIRL
ILH,ILL
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable
interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on in-
terrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should
be executed before setting IMF="1".
EF15
IL15
15
15
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not exe-
cute normally on interrupt service routine. However, if using multiple interrupt on interrupt service rou-
tine, manipulating EF or IL should be executed before setting IMF="1".
EF15 to EF4
EF14
IL14
DI
LDW
:
:
EI
unsigned int _io (3AH) EIRL;
_DI();
EIRL = 10100000B;
:
_EI();
IL15 to IL2
14
14
IMF
EF13
IL13
13
13
EIRH (003BH)
EF12
IL12
ILH (003DH)
(EIRL), 1110100010100000B
12
12
Individual-interrupt enable flag
(Specified for each bit)
Interrupt master enable flag
Interrupt latches
EF11
IL11
11
11
EF10
IL10
10
10
Page 33
EF9
IL9
9
9
at RD
0: No interrupt request
1: Interrupt request
EF8
IL8
8
8
0:
1:
0:
1:
/* 3AH shows EIRL address */
; IMF ← 0
; EF15 to EF13, EF11, EF7, EF5 ← 1
Note: IMF should not be set.
; IMF ← 1
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
EF7
IL7
7
7
EF6
IL6
6
6
EF5
IL5
5
5
at WR
0: Clears the interrupt request
1: (Interrupt latch is not set.)
EIRL (003AH)
ILL (003CH)
EF4
IL4
4
4
(Initial value: 00000000 000000**)
(Initial value: 00000000 0000***0)
IL3
3
3
TMP86FH46BNG
IL2
2
2
1
1
IMF
0
R/W
0
R/W