tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 132

• Manufacturer Part Number: tmp86fh46bng
• Description: 8 Bit Microcontroller Tlcs-870/c Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.3
Function
(2)
(3)
SIORDB, SIOSR<RXF> is cleared to “0”.
level by an automatic-wait function when all of the bit set in the data has been transmitted.
ing the received data from SIORDB, or reading the received data from SIORDB after writing the
next data to SIOTDB. Then, transmit/receive operation is restarted after maximum 1 cycle of serial
clock. In external clock operation, reading the received data from SIORDB and writing the next da-
ta to SIOTDB must be finished before the shift operation of the next data begins.
curs immediately after shift operation is started. When the transmit error occurred,
SIOSR<TXERR> is set to “1”. If received data is not read out from SIORDB before next shift oper-
ation starts after setting SIOSR<RXF> to “1”, receive error occurs immediately after shift operation
is finished. When the receive error has occurred, SIOSR<RXERR> is set to “1”.
When data is written to SIOTDB, SIOSR<TXF> is cleared to “0” and when a data is read from
In internal clock operation, in case of the condition described below, the serial clock stops to “H”
The automatic wait function is released by writing the next transmit data to SIOTDB after read-
If the transmit data is not written to SIOTDB after SIOSR<TXF> is set to “1”, transmit error oc-
There are two ways for stopping the transmit/receive operation.
During the transmit/receive operation
Stopping the transmit/receive operation
・ Next transmit data is not written to SIOTDB after reading a received data from SIORDB.
・ Received data is not read from SIORDB after writing a next transmit data to SIOTDB.
・ Neither SIOTDB nor SIORDB is accessed after transmission.
・ The way of clearing SIOCR1<SIOS>.
・ The way of setting SIOCR1<SIOINH>.
transfer of the data is finished. When transmit/receive operation is finished, SIOSR<SIOF>
is cleared to “0” and SO pin is kept in high level. In external clock operation,
SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is set to “1” by beginning
next transfer.
“1”. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register
are initialized.
When SIOCR1<SIOS> is cleared to “0”, transmit/receive operation is stopped after all
Transmit/receive operation is stopped immediately after SIOCR1<SIOINH> is set to
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