tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 75
tmp86fh46bng
Manufacturer Part Number
tmp86fh46bng
Description
8 Bit Microcontroller Tlcs-870/c Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86FH46BNG.pdf
(216 pages)
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6.3.4
tempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
hardware is reset. The reset time is maximum 24/fc [s] (1.5 μs @ fc = 16.0 MHz).
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an at-
When an address trap reset request is generated, the RESET pin outputs a low-level signal and the internal
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-
frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have in-
accuracies upon start of the high-frequency clock oscillator, the reset time should be considered as
an approximate value because it has slight errors.
Page 57
TMP86FH46BNG
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